The present invention generally relates to semiconductor devices and methods of producing semiconductor devices and, more particularly, to a semiconductor device such as a bipolar transistor having a means for connecting a collector layer of the bipolar transistor to a collector electrode or another circuit element, and a method of producing such a semiconductor device.
Conventionally, a bipolar transistor is provided with a device isolation structure such as a U-groove and a pn junction, for the purpose of isolating the bipolar transistor from other elements. A relatively thick field oxide layer is provided in order to reduce the capacitance between a base electrode and a collector layer, and in addition, a collector buried layer having a high impurity concentration is provided so as to connect the collector layer to a collector electrode at a low resistance.
A description will be given of a method of producing an example of a conventional bipolar transistor, by referring to FIGS. 1A through 1F.
As shown in FIG. 1A, n-type impurities are injected into a p-type semiconductor substrate 21 to form an n.sup.+ -type buried layer 22, and an n-type layer 23 is epitaxially grown on the n.sup.+ -type buried layer 22.
Then, silicon nitride layers 24 and 25 are respectively formed in a region where the transistor is to be formed and in a region where a collector electrode of the transistor is to be formed.
Next, as shown in FIG. 1B, the semiconductor substrate 21 formed with the silicon nitride layers 24 and 25 is oxidized to form a LOCOS type field oxide layer 26.
As shown in FIG. 1C, a U-groove 27 which penetrates the field oxide layer 26 and reaches the semiconductor substrate 21 is formed. This U-groove 27 penetrates the field oxide layer 26 which defines the outer periphery of the transistor. Hence, the region where the transistor is to be formed and the region where the collector electrode is to be formed are isolated from other regions. A silicon oxide layer 28 is thereafter formed on the inner surface of the U-groove 27.
Next, as shown in FIG. 1D, a polysilicon layer 29 is formed on the surface of the semiconductor substrate 21, including the inside of the U-groove 27, by a chemical vapor deposition (CVD).
Thereafter, as shown in FIG. 1E, the polysilicon layer 29 is polished to obtain a planarized surface, and the polished polysilicon layer 29 is further subjected to a controlled etching so as that the polysilicon layer 29 only remains inside the U-groove 27. In addition, the silicon nitride layers 24 and 25 are removed.
The top of the polysilicon layer 29 inside the U-groove 27 is oxidized to form a silicon oxide cap 30.
Therefore, a transistor region 31 in which the transistor is to be formed and a collector electrode region 32 in which the collector electrode is to be formed, are respectively formed by the above described process.
Next, as shown in FIG. 1F, p-type impurities and n-type impurities are successively injected into the transistor region 31 to form a base layer 33 and an emitter layer 34 of the transistor. In addition, n-type impurities are injected into the collector electrode region 32 to form a low resistance n.sup.++ -type region 35 which reaches the buried layer 22.
A base electrode 37, an emitter electrode 38 and a collector electrode 36 are respectively formed on the base layer 33, the emitter layer 34 and the low resistance n.sup.++ -type region 35.
However, the conventional method of producing the bipolar transistor has the following problems.
First, the collector layer must be formed by an epitaxial growth.
Second, since the collector layer is epitaxially grown on the collector buried layer, it is impossible to make the impurity concentration of the buried layer sufficiently high because of the need to maintain satisfactory crystal properties of the epitaxially grown collector layer. For this reason, the resistance between the collector layer and the collector electrode is relatively large.
Third, since the collector layer and the semiconductor substrate make contact over a relatively wide area, the capacitance between the collector layer and the semiconductor substrate is relatively large, thereby preventing a high-speed operation of the transistor.
Fourth, an isolating means such as a U-groove and a pn junction must be formed with a high accuracy in order to provide the necessary device isolation.
Fifth, it is essential to provide the field oxide layer in order to reduce the capacitance between the base electrode and the collector layer. However, when the LOCOS type field oxide layer is employed, the transistor region is relative deep and enlarged. As a result, the capacitance between the collector and base becomes relatively large, thereby preventing a high-speed operation of the transistor.
In other words, there are two factors limiting the operation speed of the bipolar transistor, namely, the base resistance and the base-collector (pn junction) capacitance. In order to reduce the base-collector capacitance so as to improve the operation speed, it is necessary to make the thickness of the LOCOS type field oxide layer large and reduce the area occupied by the bipolar transistor. However, the two cannot be satisfied simultaneously in a satisfactory manner. That is, when the LOCOS type field oxide layer is made thick, the so-called bird's beak is formed on the side of the field oxide layer, and the bird's beaks of adjacent field oxide layer portions connect in extreme cases, thereby making it impossible to form a transistor region between the adjacent field oxide layer portions. For this reason, it is difficult to control the width between the sides of the adjacent field oxide layer portions. Therefore, in order to control the widths of transistor region and the collector electrode region with a high accuracy, it would be preferable not to employ the LOCOS.